FPGA Design Creation and Simulation. Active-HDL™ is a Windows® based, integrated FPGA Design Creation and Simulation solution for team-based environments. Active-HDL’s Integrated Design Environment (IDE) includes a full HDL and graphical design tool suite and RTL/gate-level mixed-language simulator for rapid deployment and verification of FPGA designs.
References in zbMATH (referenced in 2 articles )
Showing results 1 to 2 of 2.
- Belan, S.N.; Motornyuk, R.L.: Extraction of characteristic features of images with the help of the Radon transform and its hardware implementation in terms of cellular automata (2013)
- Ditmar, Johan; Mckeever, Steve; Wilson, Alex: Area optimisation for field-programmable gate arrays in systemc hardware compilation (2008) ioport