The gem5 Simulator System. A modular platform for computer system architecture research. The gem5 simulator is a modular platform for computer system architecture research, encompassing system-level architecture as well as processor microarchitecture.
Keywords for this software
References in zbMATH (referenced in 7 articles )
Showing results 1 to 7 of 7.
- Valsan, Prathap Kumar; Yun, Heechul; Farshchi, Farzad: Addressing isolation challenges of non-blocking caches for multicore real-time systems (2017)
- Altenbernd, Peter; Gustafsson, Jan; Lisper, Björn; Stappert, Friedhelm: Early execution time-estimation through automatically generated timing models (2016)
- Wu, Zheng Pei; Pellizzoni, Rodolfo; Guo, Danlu: A composable worst case latency analysis for multi-rank DRAM devices under open row policy (2016)
- Altmeyer, Sebastian; Cucu-Grosjean, Liliana; Davis, Robert: Static probabilistic timing analysis for real-time systems using random replacement caches (2015)
- Ma, Jianliang; Yu, Licheng; Ye, John M.; Chen, Tianzhou: MCMG simulator: A unified simulation framework for CPU and graphic GPU (2015)
- Fu, Weiwei; Liu, Li; Chen, Tianzhou: Direct distributed memory access for CMPs (2014) ioport
- Lampka, Kai; Giannopoulou, Georgia; Pellizzoni, Rodolfo; Wu, Zheng; Stoimenov, Nikolay: A formal approach to the WCRT analysis of multicore systems with memory contention under phase-structured task sets (2014)
Further publications can be found at: http://www.gem5.org/Publications