The AIDA framework implements an automatic analog IC design flow from a circuit-level specification to a physical layout description. The circuit-level synthesis is done by AIDA-C, and after the circuit-level design, AIDA-L takes the device sizes and the best floorplan, and generates the complete layout, which is then saved as a GDSII stream format. AIDA-C is a circuit-level synthesizer supported by state-of-the-art multi-objective optimization kernels, where the robustness of the solutions is attained by considering user-defined worst case corners, that account for process variations and(or) PVT corners. The circuit’s performance is measured using Spectre®, Eldo® or HSPICE® electrical circuit simulators.
References in zbMATH (referenced in 1 article )
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- Lourenço, Ricardo; Lourenço, Nuno; Horta, Nuno: AIDA-CMK: multi-algorithm optimization kernel applied to analog IC sizing (2015)
Further publications can be found at: http://www.aidasoft.com/Publications