TILOS
TILOS: A posynomial programming approach to transistor sizing. A new transistor sizing algorithm, which couples synchronous timing analysis with convex optimization techniques, is presented. Let A be the sum of transistor sizes, T the longest delay through the circuit, and K a positive constant. Using a distributed RC model, each of the following three programs is shown to be convex: 1) Minimize A subject to T < K. 2) Minimize T subject to A < K. 3) Minimize AT K . The convex equations describing T are a particular class of functions called posynomials. Convex programs have many pleasant properties, and chief among these is the fact that any point found to be locally optimal is certain to be globally optimal TILOS (Timed Logic Synthesizer) is a program that sizes transistors in CMOS circuits. Preliminary results of TILOS’s transistor sizing algorithm are presented.
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References in zbMATH (referenced in 8 articles )
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Sorted by year (- Purushothaman, A.; Parikh, Chetan D.: A new delay model and geometric programming-based design automation for latched comparators (2015) ioport
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- Kim, Seung-Jean; Boyd, Stephen P.; Yun, Sunghee; Patil, Dinesh D.; Horowitz, Mark A.: A heuristic for optimizing stochastic activity networks with applications to statistical digital circuit sizing (2007)
- Szegedy, Christian: Some applications of the weighted combinatorial Laplacian (2005)