Handel-C is a high-level programming language which targets low-level hardware, most commonly used in the programming of FPGAs. It is a rich subset of C, with non-standard extensions to control hardware instantiation with an emphasis on parallelism. Handel-C is to hardware design what the first high-level programming languages were to programming CPUs. Unlike many other design languages that target a specific architecture Handel-C can be compiled to a number of design languages and then synthesised to the corresponding hardware. This frees developers to concentrate on the programming task at hand rather than the idiosyncrasies of a specific design language and architecture.

References in zbMATH (referenced in 42 articles )

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  1. Nambiar, Vishnu P.; Balakrishnan, Sathivellu; Khalil-Hani, Mohamed; Marsono, M.N.: HW/SW co-design of reconfigurable hardware-based genetic algorithm in FPGAs applicable to a variety of problems (2013) ioport
  2. Chitty, Darren M.: Fast parallel genetic programming: multi-core CPU versus many-core GPU (2012) ioport
  3. Martínez, Raúl; Claver, José M.; Alfaro, Francisco J.; Sánchez, José L.: Hardware implementation study of several new egress link scheduling algorithms (2012) ioport
  4. Perna, Juan; Woodcock, Jim: Mechanised wire-wise verification of Handel-C synthesis (2012)
  5. Zain-ul-Abdin; Svensson, Bertil: Occam-pi for programming of massively parallel reconfigurable architectures (2012) ioport
  6. Ahmed, O.; Areibi, S.; Chattha, K.; Kelly, B.: PCIU: hardware implementations of an efficient packet classification algorithm with an incremental update capability (2011) ioport
  7. Butterfield, Andrew: A denotational semantics for Handel-C (2011)
  8. Rahmani, Hossein; Bonyadi, Mohammad Reza; Momeni, Amir; Moghaddam, Mohsen Ebrahimi; Abbaspour, Maghsoud: Hardware design of a new genetic based disk scheduling method (2011)
  9. Butterfield, Andrew (ed.): Unifying theories of programming. Second international symposium, UTP 2008, Dublin, Ireland, September 8--10, 2008. Revised selected papers (2010)
  10. Fischaber, Scott; Woods, Roger; McAllister, John: SoC memory hierarchy derivation from dataflow graphs (2010) ioport
  11. Nguyen, Van; Kearney, David; Gioiosa, Gianpaolo: An extensible, maintainable and elegant approach to hardware source code generation in Reconfig-P (2010)
  12. Perna, Juan Ignacio; Woodcock, Jim: UTP semantics for Handel-C (2010)
  13. Plaza, Antonio; Plaza, Javier; Vegas, Hugo: Improving the performance of hyperspectral image and signal processing algorithms using parallel, distributed and specialized hardware-based systems (2010) ioport
  14. Bonato, Vanderlei; Marques, Eduardo; Constantinides, George A.: A floating-point extended Kalman filter implementation for autonomous mobile robots (2009) ioport
  15. Cheong, Lee Sing; Lin, Feng; Seah, Hock Soon; Qian, Kemao; Zhao, Feng; Thong, Patricia S.P.; Soo, Kee Chee; Olivo, Malini; Kung, Sun-Yuan: Embedded computing for fluorescence confocal endomicroscopy imaging (2009) ioport
  16. Fabiani, Erwan: Experiencing a problem-based learning approach for teaching reconfigurable architecture design (2009) ioport
  17. Machado, Patricia D. L. (ed.): Proceedings of the 11th Brazilian symposium on formal methods (SBMF 2008) Salvador, Brazil, August 26--29, 2008 (2009)
  18. Perna, Juan Ignacio; Woodcock, Jim: Mechanised wire-wise verification of Handel-C synthesis (2009)
  19. Prieto, Miguel S.; Allen, Alastair R.: A hybrid system for embedded machine vision using FPGAs and neural networks (2009) ioport
  20. Botella, Guillermo; Rodríguez, Manuel; García, Antonio; Ros, Eduardo: Neuromorphic configurable architecture for robust motion estimation (2008) ioport

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