SESC is a cycle accurate architectural simulator. It models a very wide set of architectures: single processors, CMPs, PIMs, and thread level speculation. SESC started as the pet project of Jose Renau while doing his PhD at Urbana-Champaign in the IACOMA group. Currently, he is a new faculty at University of California, Santa Cruz.
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References in zbMATH (referenced in 1 article )
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- Suri, Tameesh; Aggarwal, Aneesh: Improving adaptability and per-core performance of many-core processors through reconfiguration (2010)