ABC: An Academic Industrial-Strength Verification Tool. ABC is a public-domain system for logic synthesis and formal verification of binary logic circuits appearing in synchronous hardware designs. ABC combines scalable logic transformations based on And-Inverter Graphs (AIGs), with a variety of innovative algorithms. A focus on the synergy of sequential synthesis and sequential verification leads to improvements in both domains. This paper introduces ABC, motivates its development, and illustrates its use in formal verification.
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References in zbMATH (referenced in 10 articles )
Showing results 1 to 10 of 10.
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- Sen, Alper; Aksanli, Baris; Bozkurt, Murat: Speeding up cycle based logic simulation using graphics processing units (2011)
- Brayton, Robert; Mishchenko, Alan: ABC: an academic industrial-strength verification tool (2010)