HDL Coder™ generates portable, synthesizable Verilog® and VHDL® code from MATLAB® functions, Simulink® models, and Stateflow® charts. The generated HDL code can be used for FPGA programming or ASIC prototyping and design. HDL Coder provides a workflow advisor that automates the programming of Xilinx® and Altera® FPGAs. You can control HDL architecture and implementation, highlight critical paths, and generate hardware resource utilization estimates. HDL Coder provides traceability between your Simulink model and the generated Verilog and VHDL code, enabling code verification for high-integrity applications adhering to DO-254 and other standards.
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References in zbMATH (referenced in 2 articles )
Showing results 1 to 2 of 2.
- Hartley, Edward N.; Maciejowski, Jan M.: Field programmable gate array based predictive control system for spacecraft rendezvous in elliptical orbits (2015)
- Apopei, B.; Dodd, T.J.: Automatic parallelisation for LTI MIMO state space systems using FPGAs. An optimisation for cost & performance (2012) ioport