SoCLib is an open platform for virtual prototyping of multi-processors system on chip (MP-SoC). The project started as an ANR-founded project. It is now maintained at Lip6. The core of the platform is a library of SystemC simulation models for virtual components (IP cores). The main concern is true interoperability between the SoCLib IP cores. All simulation models are written in SystemC, and can be simulated with the standard SystemC simulation environment. Two types of models are available for each IP-core: CABA (Cycle Accurate / Bit Accurate), TLM-DT (Transaction Level Modeling with Distributed Time). All simulation models and most associated tools are distributed as free software.
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References in zbMATH (referenced in 1 article )
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- Meunier, Quentin L.; Pétrot, Frédéric: Lightweight transactional memory systems for NoCs based architectures: design, implementation and comparison of two policies (2010)
Further publications can be found at: http://www.soclib.fr/trac/dev/wiki/PapersAndPublications