ISDL: An instruction set description language for retargetability and architecture exploration. We present the Instruction Set Description Language, ISDL, a machine description language used to describe target architectures to a set of retargetable design tools including compilers and simulators. Such tools enable the design of embedded system processors by supporting the exploration of the architecture design space. The features and flexibility of ISDL enable the description of a wide variety of architectures with emphasis on VLIW architectures. ISDL explicitly supports constraints that define valid operation groupings within an instruction, thus increasing the range of specifiable architectures and resulting in concise and intuitive descriptions. Furthermore, a single ISDL description supports the automatic generation or retargeting of all of the design evaluation tools. This paper presents the structure and features of ISDL and describes how the information in an ISDL description may be used to retarget or generate assemblers, disassemblers, compilers, simulators, and hardware models. In addition, it compares ISDL to various other machine description languages that are being used for embedded processor design. Various complications that arose while describing real-world architectures (which include a powerful seven-way VLIW processor and the Motorola 56000 DSP) and the solutions to these complications are also presented.

References in zbMATH (referenced in 10 articles , 1 standard article )

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  1. Mei, B.; De Sutter, B.; Vander Aa, T.; Wouters, M.; Kanstein, A.; Dupont, S.: Implementation of a coarse-grained reconfigurable media processor for AVC decoder (2008)
  2. Ceng, Jianjiang; Sheng, Weihua; Hohenauer, Manuel; Leupers, Rainer; Ascheid, Gerd; Meyr, Heinrich; Braun, Gunnar: Modeling instruction semantics in ADL processor descriptions for C compiler retargeting (2006)
  3. Cockshott, Paul; Michaelson, Greg: Orthogonal parallel processing in Vector Pascal (2006)
  4. Azevedo, Rodolfo; Rigo, Sandro; Bartholomeu, Marcus; Araujo, Guido; Araujo, Cristiano; Barros, Edna: The ArchC architecture description language and tools (2005)
  5. Mishra, Prabhat; Dutt, Nikil D.: Functional verification of programmable embedded architectures. A top-down approach. (2005)
  6. Yang, Hoonmo; Lee, Moonkey: Embedded processor validation environment using a cycle-accurate retargetable instruction-set simulator (2005)
  7. Zaccaria, Vittorio; Sami, Mariagiovanna; Sciuto, Donatella; Silvano, Cristina: Power estimation and optimization methodologies for VLIW-based embedded systems (2003)
  8. Hoffmann, Andreas; Meyr, Heinrich; Leupers, Rainer: Architecture exploration for embedded processors with LISA (2002)
  9. Qin, Wei; Rajagopalan, Subramanian; Vachharajani, Manish; Wang, Hangsheng; Zhu, Xinping; August, David; Keutzer, Kurt; Malik, Sharad; Peh, Li-Shiuan: Design tools for application specific embedded processors (2002)
  10. Hadjiyiannis, George; Hanono, Silvina; Devadas, Srinivas: ISDL: An instruction set description language for retargetability and architecture exploration (2001)