SDAARC. A self distributing associative architecture (Diss. 2001) This PhD dissertation extends the ideas of cache only memory architecture to a self distributing associative architecture in which both the data and the computation are distributed. The challenge is to design a computer architecture which determines the parallelism in a program and distributes the program in such a way that the parallelism is exploited without a big investment in programmer time. Parallelism is enacted by communicating objects that migrate through the system. Two classes of objects occur, either data containers or frames. Two subclasses exist, either microframes or routing frames. A C++ or C sequential program is converted into a data flow description giving rise to a microthread version that uses Cache Only Memory Architecture (COMA). COMA is used to implement the migration of microframes to appropriate sites followed by execution of the microframes at those sites when all data are present and the microframe is authorized to execute. The granularity of a microthread/microframe implementation determines the amount of parallelism that can be obtained and the amount of communication that must be imbedded in the microframes.par Two self distributing associative architecture simulators are described: a Java based simulator and a C++ parallel virtual machine simulator. Benchmark matrix by matrix multiplication simulations and vector by matrix multiplications are presented. The simulators have many built in monitor functions that provide comparisons of associativity, frame size, run time, etc. Tables and graphs of associativities of 1, 2, 4, 8, and 16 with block sizes of 1, 2, 4, 8 and 16 on 1, 2, 3, and 4 processors for matrix multiplications of matrices of size up to 500 by 500 are presented. This is a well written monograph with an extensive bibliography.
References in zbMATH (referenced in 1 article , 1 standard article )
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