An enhanced POLIS framework for fast exploration and implementation of I/O subsystems on CSoC platforms The increasing complexity of embedded systems and demands for quicker turn-around times require reuse of hardware and software components. Reconfigurable hardware technology opens a new implementation space where software and hardware design cycles might be very close in time and where a broader range of applications can be mapped on. The exploitation of reconfigurable platforms is often hampered by the lack of a unified software/(reconfigurable) hardware design flow. In this paper, we presented an enhancement of the POLIS framework for fast exploration and implementation of input-output sub-systems on configurable systems-on-chip (CSoCs). The designer, given the functionality of the system described in POLIS, explores different solutions at the co-design level. Those solutions that, based on the estimation of performances, violate the timing requirements are pruned without the need of any FPGA synthesis and validation steps. The explored solutions satisfying the constraints are then implemented. The automatic generation of the hardware description and the hardware-software interface make the implementation step extremely fast leading to very short system design cycles.