Minerva: Automated hardware optimization tool. A common way of determining the maximum clock frequency of a digital system is static timing analysis provided by CAD toolsets, such as Xilinx Vivado, Xilinx ISE, and Intel Quartus Prime. Finding the actual maximum clock frequency is difficult, especially in Xilinx Vivado, due to the multitude of tool options, and a complex dependence between the requested clock frequency and the actual clock frequency achieved by the tool. For example, a binary search to find maximum frequency is tedious, time-consuming, and often does not obtain the correct result. In this research, we introduce an automated hardware optimization tool called Minerva. Minerva determines the close-to-optimal settings of tools, using static timing analysis and a heuristic algorithm developed by the authors, and targets either optimal throughput or throughput-to-area (TPA) ratio. We apply Minerva to the hardware benchmarking of authenticated cipher candidates competing in the CAESAR cryptographic contest, where best TPA ratio (without any specific target for maximum clock frequency) is one metric by which winners are selected. We evaluate RTL designs of 29 Round 2 CAESAR candidates and the current standard, AES-GCM, in terms of throughput and TPA ratio. Compared to a binary search for maximum frequency, our results demonstrate up to 25% improvement in terms of throughput, and up to 38% improvement in terms of TPA ratio.
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References in zbMATH (referenced in 1 article )
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- Farahmand, Farnoud; Dang, Viet B.; Nguyen, Duc Tri; Gaj, Kris: Evaluating the potential for hardware acceleration of four NTRU-based key encapsulation mechanisms using software/hardware codesign (2019)