Uppaal is an integrated tool environment for modeling, simulation and verification of real-time systems, developed jointly by Basic Research in Computer Science at Aalborg University in Denmark and the Department of Information Technology at Uppsala University in Sweden. It is appropriate for systems that can be modeled as a collection of non-deterministic processes with finite control structure and real-valued clocks, communicating through channels or shared variables [WPD94, LPW97b]. Typical application areas include real-time controllers and communication protocols in particular, those where timing aspects are critical.

References in zbMATH (referenced in 568 articles , 3 standard articles )

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  1. Al-Bataineh, Omar; Reynolds, Mark; French, Tim: Finding minimum and maximum termination time of timed automata models with cyclic behaviour (2017)
  2. Camilleri, John J.; Schneider, Gerardo: Modelling and analysis of normative documents (2017)
  3. Daca, Przemysław; Henzinger, Thomas A.; Křetínský, Jan; Petrov, Tatjana: Faster statistical model checking for unbounded temporal properties (2017)
  4. Jaghoori, Mohammad Mahdi; de Boer, Frank; Longuet, Delphine; Chothia, Tom; Sirjani, Marjan: Compositional schedulability analysis of real-time actor-based systems (2017)
  5. Jezequel, Loïg; Lime, Didier: Let’s be lazy, we have time -- or, lazy reachability analysis for timed automata (2017)
  6. Jovanović, Aleksandra; Kwiatkowska, Marta; Norman, Gethin; Peyras, Quentin: Symbolic optimal expected time reachability computation and controller synthesis for probabilistic timed automata (2017)
  7. Neykova, Rumyana; Bocchi, Laura; Yoshida, Nobuko: Timed runtime monitoring for multiparty conversations (2017)
  8. Park, Junkil; Lee, Insup; Sokolsky, Oleg; Hwang, Dae Yon; Ahn, Sojin; Choi, Jin-Young; Kang, Inhye: A process algebraic approach to the schedulability analysis and workload abstraction of hierarchical real-time systems (2017)
  9. Rocha, Camilo; Meseguer, José; Muñoz, César: Rewriting modulo SMT and open system analysis (2017)
  10. Waez, Md Tawhid Bin; Wąsowski, Andrzej; Dingel, Juergen; Rudie, Karen: Controller synthesis for dynamic hierarchical real-time plants using timed automata (2017)
  11. Aman, Bogdan; Ciobanu, Gabriel: Modelling and verification of weighted spiking neural systems (2016)
  12. André, Étienne: Parametric deadlock-freeness checking timed automata (2016)
  13. André, Étienne; Benmoussa, Mohamed Mahdi; Choppy, Christine: Formalising concurrent UML state machines using coloured Petri nets (2016)
  14. Benerecetti, Massimo; Peron, Adriano: Timed recursive state machines: expressiveness and complexity (2016)
  15. Bérard, Béatrice; Lafourcade, Pascal; Millet, Laure; Potop-Butucaru, Maria; Thierry-Mieg, Yann; Tixeuil, Sébastien: Formal verification of mobile robot protocols (2016)
  16. Bernardeschi, Cinzia; Domenici, Andrea: Verifying safety properties of a nonlinear control by interactive theorem proving with the prototype verification system (2016)
  17. Camacho, Carlos; Llana, Luis; Núñez, Alberto: Cost-related interface for software product lines (2016)
  18. D’Argenio, Pedro R.; Hartmanns, Arnd; Legay, Axel; Sedwards, Sean: Statistical approximation of optimal schedulers for probabilistic timed automata (2016)
  19. Feo-Arenis, Sergio; Westphal, Bernd; Dietsch, Daniel; Muñiz, Marco; Andisha, Siyar; Podelski, Andreas: Ready for testing: ensuring conformance to industrial standards through formal verification (2016) ioport
  20. Ghassemi, Fatemeh; Fokkink, Wan: Model checking mobile ad hoc networks (2016)

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