The smallest ARIA module with 16-bit architecture This paper presented the smallest hardware architecture of the ARIA block cipher algorithm. A 128-bit data block was divided into eight 16-bit blocks to reduce the hardware size. The 16-bit architecture allowed two S-Boxes and 16-bit diffusion operation. We proposed a design for the substitution layer and the memory block. The proposed round key generator processed a 16-bit block of a 128-bit round key for three cycles. The proposed ARIA module with a 128-bit key comprised 6,076 equivalent gates using a $0.18-\mu $m CMOS standard cell library. It took 88 clock cycles to generate four initial values for a round key and 400 clock cycles to en/decrypt 128-bit block data. The power consumption of 16-bit ARIA was only $5.02 \mu $W at 100 kHz 1.8V.
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References in zbMATH (referenced in 9 articles , 1 standard article )
Showing results 1 to 9 of 9.
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- Li, Wei; Gu, Dawu; Li, Juanru: Differential fault analysis on the ARIA algorithm (2008)
- Wu, Wen-Ling; Zhang, Wen-Tao; Feng, Deng-Guo: Impossible differential cryptanalysis of reduced-round ARIA and Camellia (2007)
- Yang, Sangwoon; Park, Jinsub; You, Younggap: The smallest ARIA module with 16-bit architecture (2006)
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- Kwon, Daesung; Kim, Jaesung; Park, Sangwoo; Sung, Soo Hak; Sohn, Yaekwon; Song, Jung Hwan; Yeom, Yongjin; Yoon, E-Joong; Lee, Sangjin; Lee, Jaewon; Chee, Seongtaek; Han, Daewan; Hong, Jin: New block cipher: ARIA (2004)