ADVIS: A Software Package for the Design of Systolic Arrays. A methodology for mapping numerical algorithms into systolic arrays is presented in this paper. This mapping is done using a transformation function which transforms the original sequential algorithm into a suitable parallel form. A program was developed to automatically generate this transformation. We consider both the case of arbitrarily large systolic arrays as well as the more realistic case of fixed-size systolic arrays requiring algorithm partitioning. An example of the algorithm is given to present the methodology and the results obtained with the program.

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Zimmermann, Karl Heinz: Linear mappings of (n)-dimensional uniform recurrences onto (k)-dimensional systolic arrays. (1996) ioport

Kuchibhotla, Prashanth; Rao, Bhaskar D.: A methodology for fast scheduling of partitioned systolic algorithms. (1995) ioport

Schoenfeld, Mirjam; Franzen, Jens; Schwiegershausen, Markus; Pirsch, Peter: The LISA design environment for the synthesis of array processors including memories for the data transfer and faut tolerance by reconfiguration and coding techniques. (1995) ioport

Xue, Jingling: Closed-form mapping conditions for the synthesis of linear processor arrays. (1995) ioport