MediaBench: a tool for evaluating and synthesizing multimedia and communication systems. Significant advances have been made in compilation technology for capitalizing on instruction-level parallelism (ILP). The vast majority of ILP compilation research has been conducted in the context of general-purpose computing, and more specifically the SPEC benchmark suite. At the same time, a number of microprocessor architectures have emerged which have VLIW and SIMD structures that are well matched to the needs of the ILP compilers. Most of these processors are targeted at embedded applications such as multimedia and communications, rather than general-purpose systems. Conventional wisdom, and a history of hand optimization of inner-loops, suggests that ILP compilation techniques are well suited to these applications. Unfortunately, there currently exists a gap between the compiler community and embedded applications developers. This paper presents MediaBench, a benchmark suite that has been designed to fill this gap. This suite has been constructed through a three-step process: intuition and market driven initial selection, experimental measurement to establish uniqueness, and integration with system synthesis algorithms to establish usefulness.

This software is also peer reviewed by journal TOMS.

References in zbMATH (referenced in 32 articles )

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  1. Dasari, Dakshina; Nelis, Vincent; Akesson, Benny: A framework for memory contention analysis in multi-core platforms (2016)
  2. Li, Yonghui; Akesson, Benny; Goossens, Kees: Architecture and analysis of a dynamically-scheduled real-time memory controller (2016)
  3. Nagpal, Rahul; Srikant, Y.N.: Compiler-assisted energy optimization for clustered VLIW processors (2012)
  4. Kim, Hyunhee; Kim, Jihong: A leakage-aware L2 cache management technique for producer-consumer sharing in low-power chip multiprocessors (2011)
  5. Nagpal, Rahul; Srikant, Y.N.: Compiler-assisted power optimization for clustered VLIW architectures (2011)
  6. Milidonis, Athanasios; Alachiotis, Nikolaos; Porpodas, Vasileios; Michail, Harris; Panagiotakopoulos, Georgios; Kakarountas, Athanasios P.; Goutis, Costas E.: Decoupled processors architecture for accelerating data intensive applications using scratch-pad memory hierarchy (2010)
  7. Rul, Sean; Vandierendonck, Hans; De Bosschere, Koen: A profile-based tool for finding pipeline parallelism in sequential programs (2010)
  8. Suri, Tameesh; Aggarwal, Aneesh: Improving adaptability and per-core performance of many-core processors through reconfiguration (2010)
  9. Brisk, Philip; Verma, Ajay K.; Ienne, Paolo: Optimistic chordal coloring: a coalescing heuristic for SSA form programs (2009)
  10. Chang, Hoseok; Cho, Junho; Sung, Wonyong: Compiler-based performance evaluation of an SIMD processor with a multi-bank memory unit (2009)
  11. Ghodrat, Mohammad Ali; Givargis, Tony; Nicolau, Alex: Optimizing control flow in loops using interval and dependence analysis (2009)
  12. Saldanha, Lance; Lysecky, Roman: Float-to-fixed and fixed-to-float hardware converters for rapid hardware/software partitioning of floating point software applications to static and dynamic fixed point coprocessors (2009)
  13. Abderazek, Ben A.; Canedo, Arquimedes; Yoshinaga, Tsutomu; Sowa, Masahiro: The QC-2 parallel queue processor architecture (2008)
  14. Loh, Gabriel H.; Jiménez, Daniel A.: Modulo path history for the reduction of pipeline overheads in path-based neural branch predictors (2008)
  15. Lysecky, Roman: Scalability and parallel execution of warp processing: Dynamic hardware/software partitioning (2008)
  16. Galanis, Michalis D.; Dimitroulakos, Gregory; Goutis, Costas E.: Performance and energy consumption improvements in microprocessor systems utilizing a coprocessor data-path (2007)
  17. Galanis, Michalis D.; Dimitroulakos, Gregory; Goutis, Costas E.: Exploring the speedups of embedded microprocessor systems utilizing a high-performance coprocessor data-path (2007)
  18. Lee, Jung-Hoon: Next high performance and low power flash memory package structure (2007)
  19. Petrov, Peter; Orailoglu, Alex: Dynamic tag reduction for low-power caches in embedded systems with virtual memory (2007)
  20. Wen, Ye; Gurun, Selim; Chohan, Navraj; Wolski, Rich; Krintz, Chandra: Accurate and scalable simulation of network of heterogeneous sensor devices (2007)

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