The PARSEC benchmark suite: characterization and architectural implications. This paper presents and characterizes the Princeton Application Repository for Shared-Memory Computers (PARSEC), a benchmark suite for studies of Chip-Multiprocessors (CMPs). Previous available benchmarks for multiprocessors have focused on high-performance computing applications and used a limited number of synchronization methods. PARSEC includes emerging applications in recognition, mining and synthesis (RMS) as well as systems applications which mimic large-scale multithreaded commercial programs. Our characterization shows that the benchmark suite covers a wide spectrum of working sets, locality, data sharing, synchronization and off-chip traffic. The benchmark suite has been made available to the public.

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  1. Kim, Hyoseung; de Niz, Dionisio; Andersson, Björn; Klein, Mark; Mutlu, Onur; Rajkumar, Ragunathan: Bounding and reducing memory interference in COTS-based multi-core systems (2016)
  2. Cebrian, Juan M.; Jahre, Magnus; Natvig, Lasse: ParVec: vectorizing the PARSEC benchmark suite (2015)
  3. Sánchez, Daniel; Cebrián, Juan M.; García, José M.; Aragón, Juan L.: Soft-error mitigation by means of decoupled transactional memory threads (2015)
  4. Wang, Hui; Wang, Rui; Luan, Zhongzhi; Qian, Xuehai; Qian, Depei: Improving multiprocessor performance with fine-grain coherence bypass (2015)
  5. Chen, Li-Cheng; Chen, Ming-Yu; Ruan, Yuan; Huang, Yong-Bing; Cui, Ze-Han; Lu, Tian-Yue; Bao, Yun-Gang: MIMS: towards a message interface based memory system (2014)
  6. Cruz, Eduardo H.M.; Diener, Matthias; Alves, Marco A.Z.; Navaux, Philippe O.A.: Dynamic thread mapping of shared memory applications by exploiting cache coherence protocols (2014)
  7. Fu, Weiwei; Liu, Li; Chen, Tianzhou: Direct distributed memory access for CMPs (2014)
  8. Li, Jianhua; Shi, Liang; Xue, Chun Jason; Xu, Yinlong: Dual partitioning multicasting for high-performance on-chip networks (2014)
  9. Malkis, Alexander; Banerjee, Anindya: On automation in the verification of software barriers: experience report (2014)
  10. Mushtaq, Hamid; Al-Ars, Zaid; Bertels, Koen: Efficent and highly portable deterministic multithreading (DetLock) (2014)
  11. Pankratius, Victor; Adl-Tabatabai, Ali-Reza: Software engineering with transactional memory versus locks in practice (2014)
  12. Chen, Lizhong; Wang, Ruisheng; Pinkston, Timothy M.: Efficient implementation of globally-aware network flow control (2012)
  13. Hartley, Timothy D.R.; Saule, Erik; Çatalyürek, Ümit V.: Improving performance of adaptive component-based dataflow middleware (2012)
  14. Oz, Isil; Topcuoglu, Haluk Rahmi; Kandemir, Mahmut; Tosun, Oguz: Thread vulnerability in parallel applications (2012)
  15. Schwartz-Narbonne, Daniel; Weissenbacher, Georg; Malik, Sharad: Parallel assertions for architectures with weak memory models (2012)
  16. Zhou, Xu; Lu, Kai; Wang, Xiaoping; Li, Xu: Exploiting parallelism in deterministic shared memory multiprocessing (2012)
  17. Hammoud, Mohammad; Cho, Sangyeun; Melhem, Rami: C-AMTE: A location mechanism for flexible cache management in chip multiprocessors (2011)
  18. Hernández, C.; Roca, A.; Flich, J.; Silla, F.; Duato, J.: Characterizing the impact of process variation on 45 nm NoC-based CMPs (2011)
  19. Kim, Hyunhee; Kim, Jihong: A leakage-aware L2 cache management technique for producer-consumer sharing in low-power chip multiprocessors (2011)
  20. Liu, Shaoshan; Eisenbeis, Christine; Gaudiot, Jean-Luc: Value prediction and speculative execution on GPU (2011)

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