Compact hardware implementations of the block ciphers mCRYPTON, NOEKEON, and SEA. Compact hardware implementations are important for enabling security services on constrained devices like radio-frequency identification (RFID) tags or sensor nodes where chip area is highly limited. In this work we present compact hardware implementations of the block ciphers: mCrypton, NOEKEON, and SEA. Our implementations are significantly smaller in terms of chip area than the results available in related work. In case of NOEKEON, we even provide the first hardware-implementation results of this algorithm at all. Our implementations are designed as stand-alone hardware modules, contain an 8-bit interface for communication, and support encryption as well as decryption operation. We give results for different datapath widths and evaluate also the impact of using shift registers or latch-based memory instead of flip flops. The most-compact implementation of mCrypton requires 2 709 GEs when using a 130 nm CMOS process technology from Faraday. NOEKEON and SEA consume 2 880 and 2 562 GEs, respectively.
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References in zbMATH (referenced in 10 articles )
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