Petrify

Petrify is a tool for synthesis of Petri nets and asynchronous controllers. Petrify reads a Petri net and generates another bisimilar Petri net which is simpler than the original description. Initially, petrify performs a token flow analysis of the initial Petri net and produces a transition system (TS). In the initial TS, all transitions with the same label are considered as one event. The TS is then transformed and transitions relabeled to fulfill the conditions required to obtain a Petri net. Petrify is able to obtain Petri nets with some specific properties: pure, free choice, unique choice, place irredundant, etc. The Petri nets accepted by petrify can also be interpreted as Signal Transition Graphs describing the behavior of asynchronous controllers. Petrify is able to solve the Complete State Coding problem and generate a speed-independent circuit. Petrify also includes another application called draw_astg to draw Signal Transition Graphs in several graphic formats.


References in zbMATH (referenced in 21 articles )

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  1. Aalst, Wil M.P.van der; Lohmann, Niels; La Rosa, Marcello: Ensuring correctness during process configuration via partner synthesis (2012) ioport
  2. Lohmann, Niels; Wolf, Karsten: Compact representations and efficient algorithms for operating guidelines (2011)
  3. Solé, Marc; Carmona, Josep: rbminer: a tool for discovering Petri nets from transition systems (2010) ioport
  4. van der Aalst, W.M.P.; Rubin, V.; Verbeek, H.M.W.; van Dongen, B.F.; Kindler, E.; Günther, C.W.: Process mining: a two-step approach to balance between underfitting and overfitting (2010) ioport
  5. Khomenko, Victor; Schaefer, Mark; Vogler, Walter; Wollowski, Ralf: STG decomposition strategies in combination with unfolding (2009)
  6. Khomenko, Victor; Madalinski, Agnes; Yakovlev, Alex: Resolution of encoding conflicts by signal insertion and concurrency reduction based on STG unfoldings (2008)
  7. Schaefer, Mark; Vogler, Walter: Component refinement and CSC-solving for STG decomposition (2007)
  8. Frank, Uri; Kapshitz, Tsachy; Ginosar, Ran: A predictive synchronizer for periodic clock domains (2006)
  9. Khomenko, Victor; Koutny, Maciej; Yakovlev, Alex: Logic synthesis for asynchronous circuits based on STG unfoldings and incremental SAT (2006)
  10. Pastor, Enric; Peña, Marco A.; Solé, Marc: TRANSYT: A tool for the verification of asynchronous concurrent systems (2005)
  11. Schäfer, Mark; Vogler, Walter; Jančar, Petr: Determinate STG decomposition of marked graphs (2005)
  12. Tripakis, Stavros; Yovine, Sergio; Bouajjani, Ahmed: Checking timed Büchi automata emptiness efficiently (2005)
  13. Esparza, Javier: A polynomial-time algorithm for checking consistency of free-choice signal transition graphs (2004)
  14. Khomenko, Victor; Koutny, Maciej; Yakovlev, Alex: Detecting state encoding conflicts in STG unfoldings using SAT (2004)
  15. Beerel, Peter A.; Xie, Aiguo: Performance analysis of asynchronous circuits using Markov chains (2002)
  16. Carmona, Josep; Cortadella, Jordi; Pastor, Enric: Synthesis of reactive systems: Application to asynchronous circuit design (2002)
  17. Edwards, Doug; Bardsley, Andrew: Balsa: An asynchronous hardware synthesis language (2002)
  18. Josephs, Mark B.; Furey, Dennis P.: A programming approach to the design of asynchronous logic blocks (2002)
  19. Theodoropoulos, Georgios K.: Distributed simulation of asynchronous Hardware: The program driven synchronization protocol (2002)
  20. Yakovlev, Alex; Xia, Fei: Towards synthesis of asynchronous communication algorithms (2002)

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