• Xilinx

  • Referenced in 96 articles [sw07491]
  • systems integration. Xilinx has transformed from an FPGA company to an ‘All Programmable’ company, offering...
  • LED

  • Referenced in 53 articles [sw18983]
  • very compact FPGA implementation of LED and PHOTON. LED and PHOTON are new ultra-lightweight ... family optimized for Field-Programmable Gate Array (FPGA) devices. In the first architecture, we propose ... lightweight hash function PHOTON on the Xilinx FPGA series Spartan-3 (low-cost) and Artix ... efficiency and we obtain the smallest known FPGA implementation (as of today) of any hash...
  • SPIRAL

  • Referenced in 48 articles [sw00903]
  • Cell, GPU, distributed memory parallel processors, and FPGA, and has produced some of the fastest...
  • HECC

  • Referenced in 27 articles [sw03475]
  • substantially better than all previously reported FPGA-based implementations. The coprocessor for HECC over ... Block RAM on Xilinx Virtex-II FPGA, and finishes one scalar multiplication in 311μs...
  • Gaalop

  • Referenced in 28 articles [sw00313]
  • focus is on parallel target platforms like FPGA (field-programmable gate arrays) or the CUDA...
  • ModelSim

  • Referenced in 18 articles [sw11960]
  • simulator of choice for both ASIC and FPGA designs. The best standards and platform support...
  • ITER-REF

  • Referenced in 16 articles [sw10290]
  • technologies such as Field Programmable Gate Arrays (FPGA), Graphical Processing Units...
  • DoReFa-Net

  • Referenced in 11 articles [sw36246]
  • convolutions can be efficiently implemented on CPU, FPGA, ASIC and GPU, DoReFa-Net opens...
  • Janus

  • Referenced in 7 articles [sw11793]
  • Janus: An FPGA-Based System for High-Performance Scientific Computing. Janus is a modular, massively ... parallel, and reconfigurable FPGA-based computing system. Each Janus module has one computational core...
  • PHOTON

  • Referenced in 5 articles [sw13048]
  • very compact FPGA implementation of LED and PHOTON. LED and PHOTON are new ultra-lightweight ... family optimized for Field-Programmable Gate Array (FPGA) devices. In the first architecture, we propose ... lightweight hash function PHOTON on the Xilinx FPGA series Spartan-3 (low-cost) and Artix ... efficiency and we obtain the smallest known FPGA implementation (as of today) of any hash...
  • Cliffosor

  • Referenced in 6 articles [sw21063]
  • Cliffosor, an innovative FPGA-based architecture for geometric algebra. Geometric objects representation and their transformationsare ... algebra operators. A prototype implementation on an FPGA board is detailed.Initial test results show more...
  • PSIM

  • Referenced in 7 articles [sw06601]
  • simulation between PSIM and ModelSim for FPGA implementation... PsimBook: An electronic book or document with...
  • POLIS

  • Referenced in 6 articles [sw03141]
  • pruned without the need of any FPGA synthesis and validation steps. The explored solutions satisfying...
  • Alpha

  • Referenced in 6 articles [sw13717]
  • interpretation, program verification, optimization, architecture synthesis, VLSI, FPGA, systolic arrays...
  • PUFKY

  • Referenced in 4 articles [sw12225]
  • successfully evaluated on a substantial set of FPGA devices. It uses a highly optimized ring ... available resources on a low-end FPGA, of which 82% are occupied by the ROPUF...
  • Yosys

  • Referenced in 5 articles [sw31796]
  • real-world designs from the ASIC and FPGA world...
  • Active-HDL

  • Referenced in 2 articles [sw10360]
  • FPGA Design Creation and Simulation. Active-HDL™ is a Windows® based, integrated FPGA Design Creation ... simulator for rapid deployment and verification of FPGA designs...
  • CIPRNG

  • Referenced in 2 articles [sw23608]
  • Such post-processing have been implemented on FPGA and ASIC without inferring any blocs ... ratio equal to 8.5 Gbps for Zynq-FPGA and 10.9 Gbps for ASIC, being thus ... fastest FPGA generators based on chaos that can pass TestU01. In particular, it is established...
  • CAIRN 2

  • Referenced in 2 articles [sw25464]
  • CAIRN 2: an FPGA implementation of the sieving step in the number field sieve method ... sieving device “CAIRN 2” with Xilinx’s FPGA which is designed to handle ... authors know, this is the first FPGA implementation and experiment of the sieving step...