Mathematical software

ADVIS
Referenced in 11 articles [sw07925]
Software Package for the Design of Systolic Arrays. A methodology for mapping numerical algorithms into ... systolic arrays is presented in this paper. This mapping is done using a transformation function ... both the case of arbitrarily large systolic arrays as well as the more realistic case ... fixed-size systolic arrays requiring algorithm partitioning. An example of the algorithm is given...

SDEF
Referenced in 4 articles [sw12063]
SDEF Systolic Programming System. SDEF, a systolic array programming system, is presented. It is intended ... domain type database, and a systolic array simulator used to test SDEF programs. The system...

Alpha
Referenced in 6 articles [sw13717]
verification, optimization, architecture synthesis, VLSI, FPGA, systolic arrays...

AutoSA
Referenced in 1 article [sw41603]
Polyhedral Compiler for High-Performance Systolic Arrays on FPGA. While systolic array architectures have ... notoriously challenging to customize an efficient systolic array processor for a target application. Designing systolic ... arrays requires knowledge for both high-level characteristics of the application and low-level hardware ... compilation framework for generating systolic arrays on FPGA. AutoSA is based on the polyhedral framework...

HeteroCL
Referenced in 2 articles [sw41597]
targeting spatial architecture templates such as systolic arrays and stencil with dataflow architectures. Experimental results...

S4CAD
Referenced in 1 article [sw00822]
analyze a set of admissible systolic arrays for a given matrix algorithm. A systematic approach ... example, the design of a systolic structure for the transitive closure algorithm is presented...

FPQRNA
Referenced in 1 article [sw18995]
FPGA chip. We propose a systolic-like array architecture with multiple PEs (Processing Elements...

ADVIS