gem5

The gem5 Simulator System. A modular platform for computer system architecture research. The gem5 simulator is a modular platform for computer system architecture research, encompassing system-level architecture as well as processor microarchitecture.


References in zbMATH (referenced in 10 articles )

Showing results 1 to 10 of 10.
Sorted by year (citations)

  1. Wei, Xueliang; Feng, Dan; Tong, Wei; Liu, Jingning; Ye, Liuqing: NICO: reducing software-transparent crash consistency cost for persistent memory (2019)
  2. Chungha Sung, Brandon Paulsen, Chao Wang: CANAL: A Cache Timing Analysis Framework via LLVM Transformation (2018) arXiv
  3. Davis, Robert I.; Altmeyer, Sebastian; Indrusiak, Leandro S.; Maiza, Claire; Nelis, Vincent; Reineke, Jan: An extensible framework for multicore response time analysis (2018)
  4. Davis, Robert I.; Altmeyer, Sebastian; Reineke, Jan: Response-time analysis for fixed-priority systems with a write-back cache (2018)
  5. Farshchi, Farzad; Valsan, Prathap Kumar; Mancuso, Renato; Yun, Heechul: Deterministic memory abstraction and supporting multicore system architecture (2018)
  6. Singh, Amit Kumar; Geetha, K.; Vollala, Satyanarayana; Ramasubramanian, N.: Efficient utilization of shared caches in multicore architectures (2016)
  7. Altmeyer, Sebastian; Cucu-Grosjean, Liliana; Davis, Robert: Static probabilistic timing analysis for real-time systems using random replacement caches (2015)
  8. Ma, Jianliang; Yu, Licheng; Ye, John M.; Chen, Tianzhou: MCMG simulator: a unified simulation framework for CPU and graphic GPU (2015)
  9. Fu, Weiwei; Liu, Li; Chen, Tianzhou: Direct distributed memory access for CMPs (2014) ioport
  10. Lampka, Kai; Giannopoulou, Georgia; Pellizzoni, Rodolfo; Wu, Zheng; Stoimenov, Nikolay: A formal approach to the WCRT analysis of multicore systems with memory contention under phase-structured task sets (2014)


Further publications can be found at: http://www.gem5.org/Publications