Wattch: a framework for architectural-level power analysis and optimizations. Power dissipation and thermal issues are increasingly significant in modern processors. As a result, it is crucial that power/performance tradeoffs be made more visible to chip architects and even compiler writers, in addition to circuit designers. Most existing power analysis tools achieve high accuracy by calculating power estimates for designs only after layout or floorplanning are complete. In addition to being available only late in the design process, such tools are often quite slow, which compounds the difficulty of running them for a large space of design possibilities. This paper presents Wattch, a framework for analyzing and optimizing microprocessor power dissipation at the architecture-level. Wattch is 1000X or more faster than existing layout-level power tools, and yet maintains accuracy within 10% of their estimates as verified using industry tools on leading-edge designs. This paper presents several validations of Wattch’s accuracy. In addition, we present three examples that demonstrate how architects or compiler writers might use Wattch to evaluate power consumption in their design process. We see Wattch as a complement to existing lower-level tools; it allows architects to explore and cull the design space early on, using faster, higher-level tools. It also opens up the field of power-efficient computing to a wider range of researchers by providing a power evaluation methodology within the portable and familiar SimpleScalar framework.

This software is also peer reviewed by journal TOMS.

References in zbMATH (referenced in 31 articles )

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  1. Yin, Yi-Xiao; Chen, Yun-Ji; Guo, Qi; Chen, Tian-Shi: Prevention from soft errors via architecture elasticity (2014) ioport
  2. Wang, Xiao-Hang; Liu, Peng; Yang, Mei; Palesi, Maurizio; Jiang, Ying-Tao; Huang, Michael C.: Energy efficient run-time incremental mapping for 3-D networks-on-chip (2013) ioport
  3. Yang, Hoeseok; Bacivarov, Iuliana; Rai, Devendra; Chen, Jian-Jia; Thiele, Lothar: Real-time worst-case temperature analysis with temperature-dependent parameters (2013)
  4. Gauthier, Lovic; Ishihara, Tohru: Processor energy characterization for compiler-assisted software energy reduction (2012) ioport
  5. Kuehnle, Matthias; Wagner, Andre; Brito, Alisson V.; Becker, Juergen: Modeling and implementation of a power estimation methodology for systemc (2012) ioport
  6. Xie, Zi-Chao; Tong, Dong; Huang, Ming-Kai; Shi, Qin-Qing; Cheng, Xu: SWIP prediction: complexity-effective indirect-branch prediction using pointers (2012) ioport
  7. Yao, Jun; Miwa, Shinobu; Shimada, Hajime; Tomita, Shinji: A fine-grained runtime power/performance optimization method for processors with adaptive pipeline depth (2011) ioport
  8. Li, Ye; Li, Honggang; Zhang, Yuwei; Qiao, Dengyu: Packet transmission policies for battery operated wireless sensor networks (2010) ioport
  9. van Stralen, Peter; Pimentel, Andy D.: A high-level microprocessor power modeling technique based on event signatures (2010) ioport
  10. Borodin, Demid; Juurlink, B. H. H. (Ben); Hamdioui, Said; Vassiliadis, Stamatis: Instruction-level fault tolerance configurability (2009) ioport
  11. Ju, Lei; Liang, Yun; Chakraborty, Samarjit; Mitra, Tulika; Roychoudhury, Abhik: Cache-aware optimization of BAN applications (2009) ioport
  12. Jung, Sangkil; Hong, Sangjin: Network/hardware cross-layer evaluation for ROHC and packet aggregation on wireless mesh networks (2009) ioport
  13. Novo, D.; Schuster, T.; Bougard, B.; Lambrechts, A.; Van der Perre, L.; Catthoor, F.: Energy-performance exploration of a CGA-based SDR processor (2009) ioport
  14. Sun, Yu; Zhang, Wei: Improving Java performance and energy dissipation through efficient code caching (2009) ioport
  15. Flores, Antonio; Aragón, Juan L.; Acacio, Manuel E.: An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures (2008) ioport
  16. Guo, Yao; Vlassov, Vladimir; Ashok, Raksit; Weiss, Richard; Moritz, Csaba Andras: Synchronization coherence: a transparent hardware mechanism for cache coherence and fine-grained synchronization (2008)
  17. Neumann, B.; von Sydow, T.; Blume, H.; Noll, T. G.: Application domain specific embedded fpgas for flexible ISA-extension of asips (2008) ioport
  18. Sun, Han-Xin; Yang, Kun-Peng; Zhao, Yu-Lai; Tong, Dong; Cheng, Xu: CASA: A new IFU architecture for power-efficient instruction cache and TLB designs (2008) ioport
  19. Silvano, Cristina; Agosta, Giovanni; Palermo, Gianluca: Efficient architecture/compiler co-exploration using analytical models (2007) ioport
  20. Wen, Ye; Gurun, Selim; Chohan, Navraj; Wolski, Rich; Krintz, Chandra: Accurate and scalable simulation of network of heterogeneous sensor devices (2007) ioport

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