FoCs -- automatic generation of simulation checkers from formal specifications. For the foreseeable future, industrial hardware design will continue to use both simulation and model checking in the design verification process. To date, these techniques are applied in isolation using different tools and methodologies, and different formulations of the problem. This results in cumulative high cost and little (if any) cross-leverage of the individual advantages of simulation and formal verification

References in zbMATH (referenced in 20 articles , 1 standard article )

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  1. Eisner, Cindy; Fisman, Dana: Functional specification of hardware via temporal logic (2018)
  2. Bozzelli, Laura; Sánchez, César: Foundations of Boolean stream runtime verification (2016)
  3. Reinbacher, Thomas; Függer, Matthias; Brauer, Jörg: Runtime verification of embedded real-time systems (2014)
  4. Tabakov, Deian; Rozier, Kristin Y.; Vardi, Moshe Y.: Optimized temporal monitors for SystemcC (2012)
  5. Jones, Kevin D.; Konrad, Victor; Ničković, Dejan: Analog property checkers: a DDR2 case study (2010)
  6. Ben-David, Shoham; Fisman, Dana; Ruah, Sitvanit: Embedding finite automata within regular expressions (2008)
  7. Fey, Görschwin; Drechsler, Rolf: Robustness and usability in modern design flows (2008)
  8. Jin, Naiyong; Shen, Chengjie; Chen, Jun; Ni, Taoyong: Engineering of an assertion-based (PSL^\textSimple)-Verilog dynamic verifier by alternating automata (2008) ioport
  9. Maler, Oded; Nickovic, Dejan; Pnueli, Amir: Checking temporal properties of discrete, timed and continuous behaviors (2008)
  10. Katelman, Michael; Meseguer, José: A rewriting semantics for ABEL with applications to hardware/software co-design and analysis (2007)
  11. Chen, Xi; Hsieh, Harry; Balarin, Felice: Verification approach of Metropolis design framework for embedded systems (2006)
  12. Chen, Xi; Luo, Yan; Hsieh, Harry; Bhuyan, Laxmi; Balarin, Felice: Survey and taxonomy of IP address lookup algorithms (2005) ioport
  13. Tabakov, Deian; Vardi, Moshe Y.: Experimental evaluation of classical automata constructions (2005)
  14. Maler, Oded; Nickovic, Dejan: Monitoring temporal properties of continuous signals (2004)
  15. Eisner, Cindy; Fisman, Dana; Havlicek, John; Lustig, Yoad; McIsaac, Anthony; Van Campenhout, David: Reasoning with temporal logic on truncated paths. (2003)
  16. Gordon, Michael J. C.: Validating the PSL/Sugar semantics using automated reasoning (2003)
  17. Gordon, Mike; Hurd, Joe; Slind, Konrad: Executing the formal semantics of the Accellera property specification language by mechanised theorem proving (2003)
  18. Håkansson, John; Jonsson, Bengt; Lundqvist, Ola: Generating online test oracles from temporal logic specifications (2003) ioport
  19. Esparza, Javier; Schwoon, Stefan: A BDD-based model checker for recursive programs (2001)
  20. Abarbanel, Yael; Beer, Ilan; Gluhovsky, Leonid; Keidar, Sharon; Wolfsthal, Yaron: FoCs -- automatic generation of simulation checkers from formal specifications (2000)