GARNET

GARNET: A detailed on-chip network model inside a full-system simulator. Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. The interconnect power was also insignificant compared to the transistor power. With uniprocessor designs providing diminishing returns and the advent of chip multiprocessors (CMPs) in mainstream systems, the on-chip network that connects different processing cores has become a critical part of the design. Transistor miniaturization has led to high global wire delay, and interconnect power comparable to transistor power. CMP design proposals can no longer ignore the interaction between the memory hierarchy and the interconnection network that connects various elements. This necessitates a detailed and accurate interconnection network model within a full-system evaluation framework. Ignoring the interconnect details might lead to inaccurate results when simulating a CMP architecture. It also becomes important to analyze the impact of interconnection network optimization techniques on full system behavior. In this light, we developed a detailed cycle-accurate interconnection network model (GARNET), inside the GEMS full-system simulation framework. GARNET models a classic five-stage pipelined router with virtual channel (VC) flow control. Microarchitectural details, such as flit-level input buffers, routing logic, allocators and the crossbar switch, are modeled. GARNET, along with GEMS, provides a detailed and accurate memory system timing model. To demonstrate the importance and potential impact of GARNET, we evaluate a shared and private L2 CMP with a realistic state-of-the-art interconnection network against the original GEMS simple network. The objective of the evaluation was to figure out which configuration is better for a particular workload. We show that not modeling the interconnect in detail might lead to an incorrect outcome. We also evaluate Express Virtual Channels (EVCs), an on-chip network flow control proposal, in a full-system fashion. We show that in improving on-chip network latency-throughput, EVCs do lead to better overall system runtime, however, the impact varies widely across applications.


References in zbMATH (referenced in 4 articles )

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  1. Li, Jianhua; Shi, Liang; Xue, Chun Jason; Xu, Yinlong: Dual partitioning multicasting for high-performance on-chip networks (2014) ioport
  2. Wang, Danyao; Lo, Charles; Vasiljevic, Jasmina; Enright Jerger, Natalie; Steffan, J. Gregory: DART: a programmable architecture for NoC simulation on FPGAs (2014)
  3. Chen, Lizhong; Wang, Ruisheng; Pinkston, Timothy M.: Efficient implementation of globally-aware network flow control (2012) ioport
  4. Li, Bin; Zhao, Li; Iyer, Ravi; Peh, Li-Shiuan; Leddige, Michael; Espig, Michael; Lee, Seung Eun; Newell, Donald: CoQoS: Coordinating QoS-aware shared resources in NoC-based SoCs (2011) ioport