McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures. This paper introduces McPAT, an integrated power, area, and timing modeling framework that supports comprehensive design space exploration for multicore and manycore processor configurations ranging from 90nm to 22nm and beyond. At the microarchitectural level, McPAT includes models for the fundamental components of a chip multiprocessor, including in-order and out-of-order processor cores, networks-on-chip, shared caches, integrated memory controllers, and multiple-domain clocking. At the circuit and technology levels, McPAT supports critical-path timing modeling, area modeling, and dynamic, short-circuit, and leakage power modeling for each of the device types forecast in the ITRS roadmap including bulk CMOS, SOI, and doublegate transistors. McPAT has a flexible XML interface to facilitate its use with many erformance simulators. Combined with a performance simulator, McPAT enables architects to consistently quantify the cost of new ideas and assess tradeoffs of different architectures using new metrics like energy-delay-area2 product (EDA2P) and energy-delay-area product (EDAP). This paper explores the interconnect options of future manycore processors by varying the degree of clustering over generations of process technologies. Clustering will bring interesting tradeoffs between area and performance because the interconnects needed to group cores into clusters incur area overhead, but many applications can make good use of them due to synergies of cache sharing. Combining power, area, and timing results of McPAT with performance simulation of PARSEC benchmarks at the 22nm technology node for both common in-order and out-of-order manycore designs shows that when die cost is not taken into account clustering 8 cores together gives the best energy-delay product, whereas when cost is taken into account configuring clusters with 4 cores gives the best EDA2P and EDAP.

References in zbMATH (referenced in 6 articles )

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  1. Prasad, Sanjiva: Best-by-simulations: a framework for comparing efficiency of reconfigurable architectures on workloads with deadlines (2018)
  2. Martí, Daniel; Rigotti, Mattia; Seok, Mingoo; Fusi, Stefano: Energy-efficient neuromorphic classifiers (2016)
  3. Mikhail Smelyanskiy, Nicolas P. D. Sawaya, Alan Aspuru-Guzik: qHiPSTER: The Quantum High Performance Software Testing Environment (2016) arXiv
  4. Li, Jianhua; Shi, Liang; Xue, Chun Jason; Xu, Yinlong: Dual partitioning multicasting for high-performance on-chip networks (2014) ioport
  5. Liu, Peng; Fang, Lei; Huang, Michael C.: DEAM: decoupled, expressive, area-efficient metadata cache (2014) ioport
  6. Cebrián, Juan M.; Sánchez, Daniel; Aragón, Juan L.; Kaxiras, Stefanos: Efficient inter-core power and thermal balancing for multicore processors (2013) ioport