Construction techniques for systematic SEC-DED codes with single byte error detection and partial correction capability for computer memory systems This correspondence proposes three new techniques to construct a class of codes that extends the protection provided by previous single error correcting (SEC)-double error detecting (DED)-single byte error detecting (SBD) codes. The proposed codes are systematic odd-weight-column SEC-DED-SBD codes providing also the correction of any odd number of erroneous bits per byte, where a byte represents a cluster of $b$ bits of the codword that are fed by the same memory chip or card. These codes are useful for practical applications to enhance the reliability and the data integrity of byte-organized computer memory systems against transient, intermittent, and permanent failures. In particular, they represent a good tradeoff between the overhead in terms of additional check bits and the reliability improvement, due to the capability to correct at least $50%$ of the multiple errors per byte.

References in zbMATH (referenced in 18 articles , 1 standard article )

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  1. Benedicte, Pedro; Hernandez, Carles; Abella, Jaume; Cazorla, Francisco J.: HWP: hardware support to reconcile cache energy, complexity, performance and WCET estimates in multicore real-time systems (2018)
  2. Nicolaidis, Michael: On-line testing for VLSI: state of the art and trends (1998)
  3. Penzo, Luca; Sciuto, Donatella; Silvano, Cristina: Construction techniques for systematic SEC-DED codes with single byte error detection and partial correction capability for computer memory systems (1995)
  4. Fujiwara, Eiji; Kitakami, Masato: A class of error-locating codes for byte-organized memory systems (1994)
  5. Clark, W. E.; Dunning, L. A.; Rogers, D. G.: Binary set functions and parity check matrices (1990)
  6. Fuja, Tom; Heegard, Chris; Goodman, Rod: Linear sum codes for random access memories (1988)
  7. Fujiwara, Eiji; Matsuoka, Kohji: A self-checking generalized prediction checker and its use for built-in testing (1987)
  8. Okano, Hirokazu; Imai, Hideki: A construction method of high-speed decoders using ROM’s for Bose- Chaudhuri-Hocquenghem and Reed-Solomon codes (1987)
  9. Dunning, Larry A.: SEC-BED-DED codes for error control in byte-organized memory systems (1985)
  10. Er, M. C.: On generating the N-ary reflected Gray codes (1984)
  11. Kaneda, Shigeo: A class of odd-weight-column SEC-DED-SbED codes for memory system applications (1984)
  12. Kaneda, Shigeo; Fujiwara, Eiji: Single byte error correcting-double byte error detecting codes for memory systems (1982)
  13. Dao, Tich T.: SEC-DED nonbinary code for fault-tolerant byte-organized memory implemented with quaternary logic (1981)
  14. Bossen, Douglas C.; Chang, Lih C.; Chen, Chin-Long: Measurement and generation of error correcting codes for package failures (1978)
  15. Reddy, Sudhaker M.: A class of linear codes for error control in byte-per-card organized digital systems (1978)
  16. Sundberg, Carl-Erik W.: Erasure and error decoding for semiconductor memories (1978)
  17. Wakerly, John: Error detecting codes, self-checking circuits and applications (1978)
  18. Carter, William C.; McCarthy, Charles E.: Implementation of an experimental fault-tolerant memory system (1976)